ASIC Logic Design Engineer

Project overview

ASIC logic Design Engineer (Note that a good command of technical English is essential given that several members of the team are English speakers).

The key skill for this mission is RTL coding, either in SystemVerilog or VHDL.

ASIC logic design engineering.

Responsibilities

Note that a good command of technical English is essential given that several members of the team are English speakers.

The key skill for this mission is RTL coding, either in SystemVerilog or VHDL.

Profile sought

ASIC logic Design Engineer

ASIC logic design engineering.

Work environment

• participate in writing the micro-architecture specifications of the ASIC in conjunction with the high-level specification provided by the architecture team
• develop in SystemVerilog the RTL code for part of the ASIC's functions, with particular attention to code quality and genericity
• work in close collaboration with the verification team to establish a quality verification plan, and correct problems found by the verification environment developed by this team
• work in close collaboration with the physical design team to correct problems reported by this team, including regarding compliance with the target clock frequency and occupied area
• possibly participate in the validation of the ASIC once its fabrication is complete

Project details

• Start: ASAP
• Duration: 7 mois renouvelable
• Remote: hybrid
• Location: Les Clayes-sous-Bois, Île-de-France, FR
• Rate: 64-81 EUR/h
• Languages: French, English