Firmware Design Engineer

Project overview

Our client, a leading innovator in the technology industry, is seeking a passionate and skilled Hardware Design Engineer 2 to join their dynamic team. As a Hardware Design Engineer 2, you will be supporting the Memory PHY team, contributing to the development of industry-leading high-speed memory interface IPs. This role offers an exciting opportunity to work on cutting-edge memory interface designs, collaborate with diverse engineering teams, and enhance your expertise in digital and analog design.

The ideal candidate will demonstrate strong analytical skills, excellent communication, and a collaborative spirit, aligning well with our organization's commitment to innovation and inclusivity.

Job Title: Hardware Design Engineer 2

Project details

Boxborough, MA

Pay Range:

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Upon completion of waiting period, consultants are eligible for:

If this is a role that interests you and you'd like to learn more, click apply now and a recruiter will be in touch with you to discuss this great opportunity. We look forward to speaking with you!

About ManpowerGroup, Parent Company of: Manpower, Experis and Talent Solutions.

Experis is a global leader in technology services and part of the ManpowerGroup (NYSE: MAN) family of brands. We connect skilled technology professionals with meaningful opportunities where they can grow their careers, expand their expertise and make a real impact. Guided by the belief that it takes Human Ingenuity to unlock the true potential of technology, Experis helps people gain experience with leading organizations, build sought-after skills and take the next step toward a brighter future.

Backed by ManpowerGroup's 75+ years of workforce expertise and global reach across more than 70 countries and territories, Experis brings the scale, insight and opportunity to help people and businesses thrive. ManpowerGroup is consistently recognized for its commitment to inclusion, ethics and responsible business, including being named one of the World's Most Ethical Companies. Learn more at

• Design RTL for high-speed memory I/O PHY interfaces, including LPDDR and DDR IPs
• Develop digital architecture from concept to physical implementation, ensuring optimal performance
• Collaborate with architects, hardware, and firmware engineers to integrate new features
• Perform timing synthesis, physical implementation, and verification of memory interface designs
• Debug design failures, identify root causes, and work with teams to resolve issues efficiently
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
• Experience with Verilog, SystemVerilog, C, and C++ programming languages
• Strong knowledge of clocking architectures, synchronization, and CDC methodology
• Experience with synthesis, timing closure, and digital design verification tools
• Familiarity with SERDES, DDR, Memory Controller, or MAC design is preferred
• Opportunity to work on industry-leading memory interface IPs and innovative projects
• Collaborative environment supporting professional growth and development
• Engagement with a talented team of engineers and industry experts
• Hybrid work model with 2-3 days onsite to foster teamwork and collaboration
• Participation in a company committed to diversity, inclusion, and ethical practices
• Medical
• Dental Plan
• Vision Plan
• 401(k)
• Weekly Pay
• Start: flexible
• Location: Boxborough, Massachusetts, United States of America, US