Senior DFT / Test Verification Engineer (m/w/d)

Project overview

Key Responsibilities

Required Qualifications

Preferred Qualifications

• Design, implement, and optimize Design-for-Test (DFT) architectures for advanced ASIC and SoC devices, including scan insertion, scan compression, and MBIST solutions.
• Develop, generate, and analyze ATPG patterns to achieve high manufacturing test coverage and product quality.
• Perform timing analysis, test debugging, and silicon validation activities to ensure robust DFT implementation.
• Automate and enhance DFT methodologies and workflows using scripting languages such as TCL, Python, Perl, or Shell.
• Work closely with design, verification, and implementation teams throughout the ASIC/SoC development cycle.
• Proven experience in Design-for-Test (DFT), Automatic Test Pattern Generation (ATPG), and ASIC testing.
• Strong hands-on expertise in Scan Design, Scan Compression, MBIST, Static Timing Analysis (STA), and JTAG/Boundary Scan methodologies.
• Solid understanding of complex SoC architectures, IP integration, and hard macros.
• Proficiency in scripting and automation using TCL, Python, Perl, or Shell.
• Experience with high-speed interfaces and memory technologies such as PCIe Gen4/Gen5, NVMe, and LPDDR4/LPDDR5.
• Familiarity with High-Speed PHY architectures and low-power test methodologies.

Project details

• Start: ab sofort
• Remote: onsite
• Location: Böblingen, Deutschland, DE