SoC Design Verification Engineer

Project overview

This contract role supports subsystem- and SoC-level functional verification, with a strong focus on understanding, enhancing, and debugging existing SystemVerilog/UVM testbenches. The core requirements include constrained-random verification, coverage and checkers, SoC architecture and interfaces, embedded C tests, RTL simulation debugging, and regression and coverage closure. Working knowledge of Python, Perl, or shell scripting and familiarity with version control workflows are also requested; a relevant engineering degree is specified.

The supplied experience range is 5–20 years, and the location is listed as Bristol, Cambridgeshire; the description does not specify work mode or a particular product or team. The engagement is contract, and no separate nice-to-have skills are identified in the description.

Responsibilities

• Strong hands-on experience in digital design verification using System Verilog and UVM.
• Experience working with existing UVM testbenches, including modifying, extending, and debugging reusable verification components.
• Good understanding of constrained-random verification, functional coverage, assertions, scoreboards, and checkers.
• Experience in subsystem-level or SoC-level functional verification.
• Strong understanding of SoC architectures, bus protocols, register interfaces, and processor-controlled peripherals.
• Experience developing, executing, or debugging embedded C tests for processor-based SoC verification.
• Ability to debug complex RTL simulation failures using industry-standard simulators and waveform debugging tools.
• Experience executing regressions, analyzing failures, and driving functional coverage closure.
• Working knowledge of scripting languages such as Python, Perl, or shell scripting.
• Familiarity with version control systems and verification development workflows.
• Have strong practical experience in debugging and enhancing existing verification environments.
• Be comfortable understanding complex, previously developed UVM testbenches rather than relying exclusively on developing new environments from scratch.

Requirements

• Hands-on digital design verification using SystemVerilog
• UVM testbench reuse, modification, extension, and debugging
• Constrained-random verification, functional coverage, assertions, scoreboards, and checkers
• Subsystem-level or SoC-level functional verification
• SoC architecture, bus protocols, register interfaces, and processor-controlled peripherals
• Development, execution, or debugging of embedded C tests for processor-based SoC verification
• RTL simulation debugging using industry-standard simulators and waveform tools
• Regression execution, failure analysis, and functional coverage closure
• Working knowledge of Python, Perl, or shell scripting
• Familiarity with version control systems and verification development workflows
• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, VLSI, or a related discipline

Project details

• Start: flexible
• Remote: hybrid
• Location: United Kingdom, GB