Physical Design

Project overview

POSITION: Physical Design

Responsibilities

We are seeking a Physical Design contractor with strong synthesis and implementation expertise to support large, timing-critical designs at advanced technology nodes.

• Perform synthesis using Cadence Genus for large, timing-challenged designs
• Drive PPA (power, performance, area) optimization through synthesis and early implementation stages
• Develop and refine floorplans using Cadence Innovus
• Collaborate closely with RTL teams to provide timely feedback on design quality, constraints, and architectural tradeoffs
• Partner with external P&R teams to iterate toward timing closure and PPA optimization
• Identify and address timing bottlenecks early in the flow to improve convergence

Requirements

Job Facts: Contract Corp To Corp | Contract Independent | Contract W2 | 12 Months | On-site | Depends on Experience

Skills: Physical Design, ASIC, SoC, Cadence Genus, Cadence Innovus, Logic Synthesis, Physical Implementation, Floorplanning, PPA Optimization, Static Timing Analysis, STA, Timing Closure, Advanced Node, 5nm, 3nm, N5, N3, RTL, VLSI, Place and Route, Power Optimization, Performance Optimization, Area Optimization

Reference: Dice Id: 91165977 | Position Id: 9130791

• Proven experience with large-scale SoC or AI-class designs
• At least 8 years of PD experience
• Hands-on experience at advanced / cutting-edge technology nodes (e.g., N5, N3 or below)
• Strong understanding of timing closure and correlation between synthesis and implementation
• Hands-on experience with Cadence Genus and Innovus
• Ability to work cross-functionally with RTL, architecture, PD, and external implementation teams

Project details

San Jose, CA OR Austin, TX (must work onsite at one of these locations)

• Start: flexible
• Duration: 12 Months
• Remote: onsite
• Location: San Jose, CA, US, US